By Cindy Eisner, Dana Fisman
This booklet describes the valuables Specification Language PSL, lately standardized as IEEE typical 1850-2005. PSL was once built to satisfy the next specifications: effortless to benefit, write, and skim; concise syntax; carefully well-defined formal semantics; expressive energy, allowing the specification for a wide category of genuine international layout houses; identified effective underlying algorithms in simulation, in addition to formal verification. easy good points are coated, in addition to complex issues comparable to using PSL in multiply-clocked designs. a whole bankruptcy is dedicated to universal error, collected during the authors' a long time of expertise in utilizing and educating the language.
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Extra resources for A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
2 The notion of time When a Boolean assertion is embedded in code that is being run, like in the simple assertions of Java and (simulated) VHDL, the notion of time need not be deﬁned – an assertion is checked whenever the statement containing the assertion is executed. For the more complicated assertions of PSL, which ﬁrst of all stand apart from the code (so that the notion of “execution” is foreign 20 Chapter 3. Some Philosophy to them) and which second of all span multiple time steps, the notion of time must be given more consideration.
The weak versions then waive the requirement that the terminating condition eventually occur, leaving only the requirement that nothing bad must happen. The eventually! operator, however, contains no idea of a bad “something”, only a terminating condition. 34 Chapter 4. Weak vs. Strong Temporal Operators Therefore, there is no way to weaken it without emptying it completely of meaning. , there is no strong version of the operators always and never, for the opposite reason. In the case of always and never, there is no terminating condition to waive.
PSL assumes that time is discrete, that is, that time consists of a sequence of evaluation cycles. The meaning of a PSL property is deﬁned relative to such a sequence of cycles. In this book, we will refer to such a sequence of cycles as a trace. PSL does not dictate how time ticks – that is, it does not dictate how such a sequence of cycles is extracted from a design under veriﬁcation. This means that the sequence of cycles as seen by two veriﬁcation tools is not necessarily the same. For example, a cycle-based simulator sees a sequence of signal values calculated cycle-by-cycle, while an event-based simulator running on the same design sees a more detailed sequence of signal values.