Advanced ASIC Chip Synthesis using Synopsys by Himanshu Bhatnagar

By Himanshu Bhatnagar

Advanced ASIC Chip Synthesis: utilizing Synopsys® Design Compiler® actual Compiler® and PrimeTime®, Second Edition describes the complex innovations and methods used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. moreover, the full ASIC layout move technique particular for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this e-book is on real-time software of Synopsys instruments, used to strive against numerous difficulties noticeable at VDSM geometries. Readers may be uncovered to a good layout technique for dealing with complicated, sub-micron ASIC designs. value is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to format, actual synthesis, and static timing research. At each one step, difficulties comparable to every section of the layout move are pointed out, with recommendations and work-around defined intimately. moreover, an important matters similar to structure, such as clock tree synthesis and back-end integration (links to structure) also are mentioned at size. additionally, the ebook comprises in-depth discussions at the foundation of Synopsys expertise libraries and HDL coding types, specific in the direction of optimum synthesis answer.
aim audiences for this publication are working towards ASIC layout engineers and masters point scholars project complicated VLSI classes on ASIC chip layout and DFT recommendations.

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