By Himanshu Bhatnagar
Advanced ASIC Chip Synthesis: utilizing Synopsys® DesignCompiler® and PrimeTime® describes the complex suggestions and strategies used for ASIC chip synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. additionally, the total ASIC layout move method special for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this booklet is on real-time program of Synopsys instruments used to wrestle a number of difficulties visible at VDSM geometries. Readers might be uncovered to an efficient layout method for dealing with advanced, sub-micron ASIC designs. value is put on HDL coding types, synthesis and optimization, dynamic simulation, formal verification, DFT test insertion, hyperlinks to format, and static timing research. At each one step, difficulties on the topic of each one section of the layout move are pointed out, with ideas and work-arounds defined intimately. additionally, the most important matters relating to format, together with clock tree synthesis and back-end integration (links to format) also are mentioned at size. moreover, the publication includes in-depth discussions at the fundamentals of Synopsys know-how libraries and HDL coding types, distinctive in the direction of optimum synthesis recommendations.
Advanced ASIC Chip Synthesis: utilizing Synopsys® DesignCompiler® and PrimeTime® is meant for an individual who's taken with the ASIC layout method, ranging from RTL synthesis to ultimate tape-out. goal audiences for this ebook are training ASIC layout engineers and graduate scholars venture complex classes in ASIC chip layout and DFT recommendations.
From the Foreword:
`This e-book, written through Himanshu Bhatnagar, offers a accomplished review of the ASIC layout movement precise for VDSM applied sciences utilizing the Synopsis suite of instruments. It emphasizes the sensible concerns confronted by way of the semiconductor layout engineer by way of synthesis and the mixing of front-end and back-end instruments. conventional layout methodologies are challenged and designated strategies are provided to assist outline the subsequent new release of ASIC layout flows. the writer offers a number of useful examples derived from real-world occasions that may turn out priceless to training ASIC layout engineers in addition to to scholars of complicated VLSI classes in ASIC design'.
Dr Dwight W. Decker, Chairman and CEO, Conexant structures, Inc., (Formerly, Rockwell Semiconductor Systems), Newport seashore, CA, USA.
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Additional resources for Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ and PrimeTime®
Setup file set searchpath [list. 3 Pre-Layout Steps The following sub-sections illustrate the steps involved during the pre-layout phase. This includes one-pass logic synthesis with scan insertion, static timing analysis, SDF generation to perform functional gate-level simulation, and finally formal verification between the source RTL and synthesized netlist. db technology library. In order to maximize the setup-time, you may constrain the design by defming clock uncertainty for the setup-time.
This section (and the book) briefly outlines the purpose and importance of using formal verification techniques and where they can be applied. However, the syntax and usage of the commands used by Formality will not be described. Formality may be used to verify RTL against RTL, RTL against synthesized gate-level netlist, or gate-level against gate-level netlist. At this point, Formality should be used to verify the RTL against synthesized netlist to check for the functional validity of the gate-level netlist.
The pre-layout steps included initial synthesis and scan insertion of the design, along with static timing analysis, and SDF generation for dynamic simulation. In order to minimize the synthesis-layout iterations, the floorplanning and routing section stressed upon the placement of cells, with emphasis on back annotating to DC, the estimated delays extracted after global routing the design. The final section used post-layout optimization techniques to fix the hold-time violations, and to generate the final SDF for simulation.